Serial transfer of digital data has a long history but recently the interest in improving this technology has heightened. As data words and data busses grow wider and processing cheaper, it becomes increasingly desirable, indeed vital, to move digital data in serial form from one system to another, from one board to another within a system, from one chip to another on a board, and even from one core to another within a chip. In current Serializer-Deserializer (SerDes) transmitter practice, the parallel source data is loaded into a shift register and shifted out at high speed. At the receiver the reverse process takes place: data is shifted at high speed into a shift register and offloaded in parallel. This seemingly simple process has evolved into elaborate systems as more and more data are packed onto a wire.
Differential signaling is used to reduce noise and increasingly elaborate “analog front ends” (AFEs) are used to control noise and reflections on the transmission lines. Special dielectrics are used to reduce high-frequency losses. Clock phase and jitter are critical and feedback circuits are used to exactly “recover” and phase-align the desired clock. Error-correcting codes are required to achieve acceptable Bit Error Rates (BER) and these codes extract an overhead in reduced data throughput. An additional layer of coding, such as the so-called “8B/10B” code, is modulated onto the data stream to prevent excessive stretches without a transition (which would interfere with clock recovery) and to guarantee equal numbers of zeros and ones within a given interval (which removes low frequencies, improves noise immunity, and simplifies analog design). The latter codes also reduce data throughput. 8B/10B, for instance, encodes eight bits into ten bits and therefore reduces throughput 20%. On top of this, spread-spectrum clocking is used to reduce electromagnetic interference (EMI).
Current SerDes practice, for all its complications, is still basically a serial bit stream. As shown in FIGS. 1 and 2, a zero or one lasts one clock period (T) and is followed by a zero or one in the next clock period. If there is no transition between bits on a given clock, the waveform must wait for the next clock before there can be a transition for transmission.